• DocumentCode
    1686766
  • Title

    STAMP: A universal algorithmic model for next-generation multithreaded machines and systems

  • Author

    Dubois, Michel ; Lee, Hyunyoung

  • Author_Institution
    Dept. of Electr. Eng., Southern California Univ., Los Angeles, CA
  • fYear
    2008
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    We propose a generic algorithmic model called STAMP (Synchronous, Transactional, and Asynchronous Multi- Processing) as a universal performance and power complexity model for multithreaded algorithms and systems. We provide examples to illustrate how to design and analyze algorithms using STAMP and how to apply the complexity estimates to better utilize CMP(Chip MultiProcessor)-based machines within given constraints such as power.
  • Keywords
    multi-threading; multiprocessing programs; STAMP; asynchronous multiprocessing; chip multiprocessor-based machines; next-generation multithreaded machines; next-generation multithreaded systems; power complexity model; transactional multiprocessing; universal algorithmic model; Algorithm design and analysis; Computer science; Context modeling; Energy consumption; Hardware; Large-scale systems; Performance analysis; Power system modeling; Process design; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on
  • Conference_Location
    Miami, FL
  • ISSN
    1530-2075
  • Print_ISBN
    978-1-4244-1693-6
  • Electronic_ISBN
    1530-2075
  • Type

    conf

  • DOI
    10.1109/IPDPS.2008.4536385
  • Filename
    4536385
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1686766