Implementation of an FPGA-based low-power video processing module for a head-mounted display system

Portable head-mounted display (HMD) systems must balance functionality against battery life. To maximize operation time between battery recharges, we present a power-optimized field-programmable gate array (FPGA)-based implementation of an HMD video processing system. In this paper, power reduction is achieved using adaptive hardware-based sleep mode; this technique is performed by applying clock gating to the embedded microprocessor in our HMD system during idle times. Clock gating is available in many FPGA devices. Resource utilization and power dissipation results for the FPGA-based system are presented for different performance configurations.