The PowerPC 603 microprocessor: an array built-in self test mechanism

Author

Hunter, Charles ; Slaton, J. ; Eno, J. ; Jessani, R. ; Dietz, Carl

Author_Institution

Somerset Design Center, Motorola Inc., Austin, TX, USA

fYear

34608

Firstpage

388

Lastpage

394

Abstract

The PowerPC 603 microprocessor is designed for low power, low cost computing applications. A RAM built-in-self-test (BIST) implementation tests the split 8k instruction and data caches and the tag arrays. The design is constrained by the need to minimize area overhead while providing high test coverage and rapid at-speed testing. The solution encompasses a novel state machine design built using logic synthesis tools. This paper presents the RAM BIST design implemented on the PowerPC 603 microprocessor

Keywords

built-in self test; computer testing; integrated circuit testing; logic design; logic testing; microprocessor chips; random-access storage; BIST; BIST interface; PowerPC 603 microprocessor; RAM; RAM BIST design; area overhead; array built-in self test; at-speed testing; data caches; logic synthesis tools; pattern generators; tag arrays; Automatic testing; Built-in self-test; Costs; Logic arrays; Logic design; Logic testing; Microprocessors; Random access memory; Read-write memory; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1994. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-2103-0

Type

conf

DOI

10.1109/TEST.1994.527980

Filename

527980

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1688313