Design and implementation of high speed sense amplifier

Paper examines the delay of Current Mirror Sense amplifier by chang of Vdd and Vtn and also verifies the various result Like Slew Rate, Noise Margin, Power consumption, Voltage Gain, CMRR, Offset Voltage Sensitivity at 180 nm technology. Paper shows that when Vdd increases circuit Ability to avoid the noise increases but power consumption are increases and accordingly current consumption are also increases. Simulation result shows that speed of Sense Amplifier are decreases but interesting improvement in current consumption.