DocumentCode :
1689026
Title :
Defect classes-an overdue paradigm for CMOS IC testing
Author :
Hawkins, Charles F. ; Soden, Jerry M. ; Righter, Alan W. ; Ferguson, F. Joel
Author_Institution :
Dept. of Electr. & Comput. Eng., New Mexico Univ., Albuquerque, NM, USA
fYear :
34608
Firstpage :
413
Lastpage :
425
Abstract :
The IC test industry has struggled for move than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS ICs that uses defect classes based on measured defect electrical properties. Defect classes differ from traditional fault models. Our defect class approach requires that the rest strategy match the defect electrical properties, while fault models require that IC defects match the fault definition. We use data from Sandia Labs failure analysis and test facilities and from public literature. We describe test pattern requirements for each defect class and propose a test paradigm
Keywords :
CMOS logic circuits; electric current measurement; failure analysis; fault diagnosis; integrated logic circuits; logic testing; CMOS IC testing; IDDQ test; IC defects; Sandia Labs; bridge defect; combinational defect; comprehensive strategy; cost; defect classes; delay defect; failure analysis; layout defect; low defect level; measured defect electrical properties; open circuit defect; sequential defect; test facilities; test paradigm; test pattern requirements; CMOS integrated circuits; CMOS technology; Circuit faults; Circuit testing; Failure analysis; Integrated circuit modeling; Integrated circuit testing; Manufacturing; Semiconductor device modeling; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
ISSN :
1089-3539
Print_ISBN :
0-7803-2103-0
Type :
conf
DOI :
10.1109/TEST.1994.527983
Filename :
527983
Link To Document :
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