Title :
Networks-in-Package; Design, Analysis and Implementation
Author :
Kim, Gawon ; Lee, Kangmin ; Kim, Jinhan ; Bae, KiCheol ; Lee, ChoonHeung ; Yoo, Hoi-Jun ; Kim, Joungho
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon
Abstract :
SiP (system-in-package) and SoC (system-on-chip) are familiar to us. In this paper, we firstly define advanced concepts of NoC (network-on-chip) and NiP (network-in-package). Design and implementation of NoC are explained and then, NiP used for NoC is designed and analyzed regarding of signal integrity and power integrity. The low-power packet-switched NoC with hierarchical star topology is designed and implemented for high-performance SoC platform. An NiP integrating four NoCs is fabricated in a 676-BGA-type package for large and scalable systems and the measured results of the NiP show perfect communications between NoCs
Keywords :
ball grid arrays; integrated circuit design; low-power electronics; network-on-chip; BGA package; NiP; hierarchical star topology; high-performance SoC; low-power packet-switched NoC; network-on-chip; networks-in-package; power integrity; signal integrity; Clocks; Electronics packaging; Frequency; Intellectual property; Large-scale systems; Logic; Network-on-a-chip; Semiconductor device measurement; Signal design; Submillimeter wave technology;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2006 IEEE
Conference_Location :
Scottsdale, AZ
Print_ISBN :
1-4244-0668-4
DOI :
10.1109/EPEP.2006.321234
