An effective performance of combinational and sequential logic cells using current source modeling

Current source model has become a good concern in logic cells. These standard cells must be presented for performing noise and delay analysis. Current source modeling is effectively considered for the traditional static timing analysis. The existing CSMs are only applicable for combinational logic cell. The proposed methods were implementing all logic cells. Logic cells can take arbitrary shapes inputs like step and ramp signals but ramp signal only applied here. In this paper described about the circuit parameters simulate in effective spice and determine the noise, time, delay waveforms with SPICE accuracy. We can able to compute the RMSE values from the SPICE and CSM voltage values. The proposed method computes the correct RMSE values from different logical circuits using CSM and compares their results.