Voltage-Driven Multilevel Programming in Phase Change Memories

In the multilevel (ML) storage approach, any single cell in a memory array is programmed to one among n>2 predetermined different states. To exploit the ML approach in the case of phase change memories (PCMs), it is necessary to accurately program the active chalcogenide layer to a number of different partially crystallized states so as to precisely allocate the electrical resistance of the cell in the range from the maximum to the minimum available value. In this paper, we experimentally investigate the characteristics of two voltage-driven programming algorithms, namely, the single-pulse and the (multi-pulse) staircase-up (SCU) programming algorithm, from a ML storage point of view. To this end, we analyze the impact of the amplitude and the time length of applied voltage pulses on the programmed resistance, showing that the SCU algorithm appears to be a promising candidate for PCM ML storage.