Perimeter quadrature-based metric for estimating FPGA fragmentation in 2D HW multitasking

This paper explains a new technique to estimate free area fragmentation, when hardware multitasking is being considered on a 2D FPGA. The importance of a good fragmentation metric is stated, as well its use as allocation heuristic and as defragmentation alarm. We present a new fragmentation metric based on the relative quadrature of the free area perimeter, showing examples of how it behaves with one or several holes and also with islands. Finally, we show how it can be used as cost function in a location selection heuristic, each time a task is loaded in the FPGA. Experimental results show that though it maintains a low complexity, this metric behaves better than most of the previous ones, discarding a lower amount of computing volume when the FPGA supports a heavy task load.