Title :
Designing “dual personality” IEEE 1149.1 compliant multi-chip modules
Author_Institution :
Eng. Res. Center, AT&T Bell Labs., Princeton, NJ, USA
Abstract :
The IEEE 1149.1 Test Access Port and Boundary-Scan Architecture Standard can be used at many different levels in the integration hierarchy of a product. However there is one level where using the standard poses some difficulty. This is multi-chip modules (MCM). This paper explores the problem and proposes a set of solutions for different classes of MCMs
Keywords :
IEEE standards; automatic testing; boundary scan testing; integrated circuit testing; logic testing; multichip modules; IEEE 1149.1 Test Access Port and Boundary-Scan Architecture Standard; MCM testing; PCB; die design; dual IEEE 1149.1 compliant multi-chip modules; hardware; integration hierarchy; multi-chip modules; passive by-pass; scan chain configuration logic; software; test signal routing; Built-in self-test; Cost function; Emulation; Functional programming; Manufacturing; Packaging; Performance evaluation; System testing; Test equipment; Wafer scale integration;
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2103-0
DOI :
10.1109/TEST.1994.527986
