• DocumentCode
    169100
  • Title

    HiTS: A High Throughput Memory Scheduling Scheme to Mitigate Denial-of-Service Attacks in Multi-core Systems

  • Author

    Shafaei, Mansour ; Yunsi Fei

  • Author_Institution
    Electr. & Comput. Eng. Dept., Northeastern Univ., Boston, MA, USA
  • fYear
    2014
  • fDate
    22-24 Oct. 2014
  • Firstpage
    206
  • Lastpage
    213
  • Abstract
    Sharing DRAM memory by multiple cores in a computer system potentially exposes the running threads on cores to denial-of-service (DoS) attacks. This issue is usually addressed by memory scheduling schemes that rotate the memory service among threads according to a certain ranking mechanism. These ranking-based schemes, however, often incur many memory banks´ row-buffer conflicts which reduce the throughput of DRAM and the entire system. This paper proposes a new ranking-based memory scheduling scheme, called HiTS, to mitigate DoS attacks in multicore systems with the lowest performance degradation. HiTS achieves these by ranking threads according to each thread´s memory usage/requirement. HiTS then enforces the ranking in a way that minimum performance overhead would occur and fairness is also balanced. The effectiveness of HiTS is evaluated by simulations with 18 different workloads running on 8- and 16-core machines. The simulation results show up to 15.8% improvements in terms of unfairness reduction and 24.1% in system throughput compared with the best existing scheduling scheme.
  • Keywords
    DRAM chips; computer network security; multiprocessing systems; DRAM memory; DoS attacks; HiTS; denial-of-service attacks; high throughput memory scheduling scheme; multicore systems; ranking-based memory scheduling scheme; Benchmark testing; Computer crime; Instruction sets; Message systems; Random access memory; Switches; Throughput; DRAM memory; denial-of-service attack; memory scheduling scheme; multi-core systems;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture and High Performance Computing (SBAC-PAD), 2014 IEEE 26th International Symposium on
  • Conference_Location
    Jussieu
  • ISSN
    1550-6533
  • Type

    conf

  • DOI
    10.1109/SBAC-PAD.2014.36
  • Filename
    6970666