HW/SW Co-Design and Implementation of Multi-Standard Video Decoding

Author

Feng, Liu ; Rui, Guo ; Shu, Shi ; Xu, Cheng

Author_Institution

Microprocessor Res. & Dev. Center, Peking Univ., Beijing

fYear

2006

Firstpage

87

Lastpage

92

Abstract

In this paper, we present a design and implementation of multi-standard video decoder, which adopts the principle of HW/SW cooperation to achieve real time video decoding process. Based on the profiling of MPEG-1/2/4 video decoding algorithms, the computational intensive IDCT and sub-pixel interpolation are figured out to implement with hardware, and the dedicated DMA channels are provided to fulfil the high throughput of MC processing. The remained decoding functions are realized with software based on a RISC CPU. The design shares the advantage of high flexibility to fulfil multi-standard processing. With the assistant hardware accelerating, the proposed video decoder can achieve the MPEG-1/2/4 D1 size (720times480) video decoding at 30 fps

Keywords

data compression; decoding; hardware-software codesign; interpolation; video coding; DMA channel; HW-SW co-design; IDCT; MPEG-video decoding algorithm; RISC CPU; inverse-discrete cosine transform; multistandard video decoder; sub-pixel interpolation; Coprocessors; Decoding; Discrete cosine transforms; Hardware; MPEG 4 Standard; Standards development; Transform coding; Video compression; Video sharing; Videoconference;

fLanguage

English

Publisher

ieee

Conference_Titel

Embedded Systems for Real Time Multimedia, Proceedings of the 2006 IEEE/ACM/IFIP Workshop on

Conference_Location

Seoul

Print_ISBN

0-7803-9783-5

Type

conf

DOI

10.1109/ESTMED.2006.321279

Filename

4115459