Muir Hardware Synthesis for Multimedia Applications

Muir hardware synthesis process used in the Abhainn design flow for optimisation and implementation of applications on FPGA-centric platforms and specifically its use for multimedia applications. Demonstrated are transformations available at the algorithmic level for an MPEG-2 encoder to reduce the memory usage and increase the throughput of the system. Also examined is the effect manipulations of the algorithm have on the final hardware architecture. Implementation of the encoder shows that results derived from a system level design approach are comparable with those derived from hand-coded implementations