Title :
Efficient test response compression for multiple-output circuits
Author :
Chakrabarty, Krishnendu ; Hayes, John P.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Abstract :
A major obstacle to achieving high fault coverage in built-in self testing (BIST) methods that employ response compression is aliasing, which occurs when a faulty circuit´s signature maps to the fault-free signature. Another problem with many compression methods is that they are inefficient for multiple-output circuits. We present data showing that in most cases, faults are sensitized to an odd number of outputs, even when reduced test sets are used. This suggests that odd-parity detection alone provides very high fault coverage. We then introduce several systematic design techniques that guarantee zero-aliasing compression for single stuck-line faults in multiple-output circuits. We present the results of applying this approach to the ISCAS combinational benchmark circuits using both reduced and pseudorandom test sets. Our experiments show that very high fault coverage (up to 100%) can be achieved with small test sets and low hardware overhead
Keywords :
automatic testing; built-in self test; combinational circuits; fault location; logic testing; performance evaluation; BIST; ISCAS combinational benchmark circuits; aliasing; built-in self testing; fault-free signature; faulty circuit; high fault coverage; multiple-output circuits; odd-parity detection; pseudorandom test sets; reduced test sets; response compression; signature maps; single stuck-line faults; test response compression; zero-aliasing compression; Automatic test pattern generation; Benchmark testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Electrical fault detection; Fault detection; Shift registers; Test pattern generators;
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2103-0
DOI :
10.1109/TEST.1994.527992