• DocumentCode
    1691366
  • Title

    High performance Pch-LDMOS transistors in wide range voltage from 35V to 200V SOI LDMOS platform technology

  • Author

    Shimamoto, Satoshi ; Yanagida, Yohei ; Shirakawa, Shinji ; Miyakoshi, Kenji ; Imai, Toshinori ; Oshima, Takayuki ; Sakano, Junichi ; Wada, Shinichiro

  • Author_Institution
    Micro Device Div., Hitachi, Ltd., Tokyo, Japan
  • fYear
    2011
  • Firstpage
    44
  • Lastpage
    47
  • Abstract
    We have developed high performance Pch-LDMOS transistors in wide range rated voltage from 35V to 200V SOI LDMOS platform technology. By applying a novel channel structure, a high saturation drain current of 172 μA/μm in the 200V Pch-LDMOS transistor was achieved, which is comparable to that of the Nch-LDMOS transistor. A low on-resistance of 3470 mΩ*mm2 was obtained while maintaining high on- and off-state breakdown voltages of -240 and -284 V. The 35V to 200V LDMOS transistors with a competitive low on-resistance were also demonstrated by layout optimization such as RESURF structure and field plate.
  • Keywords
    MOSFET; optimisation; silicon-on-insulator; RESURF structure; SOI LDMOS platform technology; field plate; high performance Pch-LDMOS transistors; high saturation drain current; novel channel structure; optimization; voltage 35 V to 200 V; wide range voltage; Harmonic analysis; Imaging; Ion implantation; Layout; Logic gates; Stress; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Power Semiconductor Devices and ICs (ISPSD), 2011 IEEE 23rd International Symposium on
  • Conference_Location
    San Diego, CA
  • ISSN
    1943-653X
  • Print_ISBN
    978-1-4244-8425-6
  • Type

    conf

  • DOI
    10.1109/ISPSD.2011.5890786
  • Filename
    5890786