Quadrature Direct Digital Frequency Synthesizer Using FPGA

Author

Saber, M. Saber ; Elmasry, M. ; Abo-Elsoud, M. Eldin

Author_Institution

Nat. Res. Inst. of Astron. & Geophys., Cairo

fYear

2006

Firstpage

14

Lastpage

18

Abstract

A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Such system is based on a classical DDFS structure. In order to avoid the high power consumption, no ROM is used but piecewise linear approximation is employed. The system is implemented using FPGA with 3.3 V supply voltage. The power consumption is 3.96 mW. The spurious-free dynamic range is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz

Keywords

approximation theory; direct digital synthesis; field programmable gate arrays; low-power electronics; piecewise linear techniques; 1.5 kHz; 3.3 V; 3.96 mW; DDFS; FPGA; field programmable gate array; low-power quadrature direct digital frequency synthesizer; piecewise linear approximation; Clocks; Communication switching; Energy consumption; Field programmable gate arrays; Frequency synthesizers; Low pass filters; Phase locked loops; Power engineering and energy; Read only memory; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Engineering and Systems, The 2006 International Conference on

Conference_Location

Cairo

Print_ISBN

1-4244-0271-9

Electronic_ISBN

1-4244-0272-7

Type

conf

DOI

10.1109/ICCES.2006.320418

Filename

4115478