Title :
Techniques for characterizing DRAMs with a 500 MHz interface
Author :
Gasbarro, James A. ; Horowitz, Mark A.
Author_Institution :
Rambus Inc., USA
Abstract :
The advent of high-bandwidth DRAMs poses a number of new challenges for test and characterization. This paper describes a collection of techniques that were used in the design and characterization of a new DRAM architecture with 500 MHz I/O signals. Methods of fixturing and calibration are presented for achieving system accuracies of better than 100 ps. Laboratory techniques for measuring critical circuit parameters such as path delay, clock jitter, current source strength, and pin capacitances are shown as well. These techniques, along with on-chip test logic, which allows the DRAM core to be tested using conventional low-speed memory test equipment, enable full characterization of high bandwidth memories
Keywords :
DRAM chips; automatic test equipment; automatic testing; calibration; critical path analysis; fault diagnosis; system buses; 500 MHz; DRAM; I/O signals; calibration; clock jitter; critical circuit parameters; current source strength; fixturing; high bandwidth memories; high-bandwidth DRAM; low-speed memory test equipment; on-chip test logic; path delay; pin capacitances; Calibration; Capacitance measurement; Circuit testing; Current measurement; Delay; Fixtures; Laboratories; Logic testing; Random access memory; Signal design;
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2103-0
DOI :
10.1109/TEST.1994.527994
