Title :
A Multi-Engine LUT-Based Synthesis Framework
Author :
Hamed, Bassem A. ; Salem, Ashraf ; Aly, Gamal M.
Author_Institution :
Comput. & Syst. Eng., Ain Shams Univ., Cairo
Abstract :
In this paper, we present a new synthesis framework. This framework, ASU-Synthesizer, is built for logic synthesis for LUT based FPGAs. The synthesis process is composed of logic optimization and technology mapping. We implemented the different categories of logic optimization algorithms. Then we used the well known technology mapping package, Flow-Map (Cong et al., 1996). We added to the framework, our online area estimator that we proposed before in (Hamed et al., 2004). This framework can be used to build any commercial synthesis tool for LUT-based designs
Keywords :
field programmable gate arrays; logic design; logic testing; table lookup; ASU-Synthesizer; FPGAs; Flow-Map; LUT-based design synthesis tool; logic optimization; logic synthesis; look-up tables; multiengine LUT-based synthesis framework; online area estimator; technology mapping; Circuit synthesis; Design optimization; Field programmable gate arrays; Logic circuits; Logic design; Network synthesis; Packaging; Prototypes; Systems engineering and theory; Table lookup;
Conference_Titel :
Computer Engineering and Systems, The 2006 International Conference on
Conference_Location :
Cairo
Print_ISBN :
1-4244-0271-9
Electronic_ISBN :
1-4244-0272-7
DOI :
10.1109/ICCES.2006.320435
