Multithreading in systolic/SIMD DSP processor arrays

Systolic arrays are efficient parallel computing structures used in digital signal processing, for solving linear algebra algorithms and other problems. The throughput of systolic arrays is bounded by “systolic cycle” length, which depends on the number of operations performed by each processing element within array. Multithreading can enhance the throughput of systolic array by interleaving independent data threads on the array thus eliminating various hazards within processing elements. We take three algorithms as a case study to show that significant speedups are possible, up to nine for four threads running simultaneously