A Self-Routing Switch Fabric Architecture on a Chip

We present a new switch fabric architecture on a chip for the next generation link speed. The advances in CMOS technologies and optical technologies have changed the design constraints of switch fabrics. The number of transistors on a chip is no longer a major issue in the switch fabric design. Processing speed and wire length have become critical as the link rate continues to increase dramatically. Noting these trends, we propose a new switch fabric that consists of switching elements in a regular tile structure. This regular structure leads to a highly pipelined and self-routing architecture. The results of the synthesized circuits show that a single chip can support 64 ports and 40 Gb/s data rate using current CMOS technologies.