Title :
CSTBT™(III) having wide SOA under high temperature condition
Author :
Fukada, Yusuke ; Suzuki, Kenji ; Takahashi, Tetsuo ; Harada, Tatsuo ; Fujii, Hidenori ; Ishizawa, Shinichi ; Yamashita, Junichi ; Donlon, John F. ; Terashima, Tomohide
Author_Institution :
Power Device Works, Mitsubishi Electr. Corp., Fukuoka, Japan
Abstract :
This paper presents high temperature performance of CSTBT™ (III) and its main parameters. The key for high temperature operation is suppressing the parasitic NPN transistor action. N+ emitter width, P+ diffusion layer depth and gate oxide thickness are main parameters for suppressing the parasitic action. The optimized 1200V CSTBT™(III) succeeded in 200°C operation without any thermal runaway or turn-off failure.
Keywords :
insulated gate bipolar transistors; power bipolar transistors; carrier stored trench gate bipolar transistor; diffusion layer depth; emitter width; gate oxide thickness; high-temperature operation; parasitic NPN transistor action; temperature 200 degC; thermal runaway; turn-off failure; voltage 1200 V; Current density; Logic gates; Resistance; Temperature dependence; Temperature measurement; Threshold voltage; Transistors;
Conference_Titel :
Power Semiconductor Devices and ICs (ISPSD), 2011 IEEE 23rd International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4244-8425-6
DOI :
10.1109/ISPSD.2011.5890808
