Title :
52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)
Abstract :
The following topics are dealt with: Ethernet and WDM technology; package electrical characterization; flip chip packaging; solder technology; reliability and test; modules; materials, transceivers and interconnects; power and EM modeling; flip-chip underfills; reliability and stress; integrated and on-chip passives; reliability and integration; package assembly modeling; process development and characterization for high density interconnects; packaging education; low cost optical packaging; dielectric, adhesive and underfill delamination and modeling; wire bonding and interconnections; substrates and dielectrics; failure analysis; RF devices and RF MEMS; interconnect modeling and characterization; electrically conductive adhesives; wafer level processing and test; Pb-free flip chip; Pb-free solder reliability; failure prediction and modeling; chip-scale and wafer-level packaging; high density and 3D interconnects; array interconnect manufacturing technology; Web-based packaging education.
Keywords :
adhesives; assembling; circuit reliability; computer aided instruction; conducting polymers; delamination; electronic engineering education; encapsulation; failure analysis; flip-chip devices; integrated circuit interconnections; integrated circuit packaging; lead bonding; local area networks; micromechanical devices; modules; semiconductor device reliability; soldering; telecommunication equipment; wavelength division multiplexing; 3D interconnects; EM modeling; Ethernet technology; Pb; Pb-free flip chip; Pb-free solder reliability; RF MEMS; RF devices; WDM technology; Web-based education; adhesive delamination; array interconnect manufacturing technology; chip-scale packaging; delamination modeling; dielectric delamination; electrically conductive adhesives; electronic components; failure analysis; failure modeling; failure prediction; flip chip packaging; flip-chip underfills; high density interconnects; integrated passives; integration reliability; interconnect modeling; low cost optical packaging; on-chip passives; package assembly modeling; package electrical characterization; packaging education; power modeling; process development; solder technology; stress reliability; substrates; transceivers; underfill delamination; wafer level processing; wafer level test; wafer-level packaging; wire bonding; Assembly; Circuit reliability; Communication equipment; Computer aided instruction; Electronics engineering education; Encapsulation; Failure analysis; Flip-chip devices; Integrated circuit interconnections; Integrated circuit packaging; Lead bonding; Local area networks; Microelectromechanical devices; Semiconductor device reliability; Soldering; Wavelength division multiplexing;
Conference_Titel :
Electronic Components and Technology Conference, 2002. Proceedings. 52nd
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-7430-4
DOI :
10.1109/ECTC.2002.1008063
