Software-defined DVB-T2 receiver using coarse-grained reconfigurable array processors

Author

Basutkar, Navneet ; Ho Yang ; Peng Xue ; Kitaek Bae ; Young-Hwan Park

Author_Institution

Samsung Adv. Inst. of Technol., Samsung Electron. Co. Ltd., Yongin, South Korea

fYear

2013

Firstpage

580

Lastpage

581

Abstract

This paper describes the feasibility of software implementation of DVB-T2 receiver with DTG-106 [1] mode using the coarse-grained reconfigurable array (CGRA) based processor. This paper focuses mainly on DVB-T2 system design and implementation of major software functions of DVB-T2 demodulator: FFT, frequency interpolation, multi-level de-interleaving, and soft-demapper. By implementing the full chain DVB-T2 software and measuring the cycle performance, we demonstrate the software implantation of DVB-T2 on dual core CGRA processor running at 400MHz.

Keywords

fast Fourier transforms; interpolation; microprocessor chips; software engineering; telecommunication computing; television broadcasting; television receivers; DTG-106 mode; DVB-T2 demodulator; FFT function; coarse-grained reconfigurable array; digital terrestrial television broadcasting system; dual core CGRA processor; fast Fourier transform; interpolation function; multilevel deinterleaving function; soft-demapper function; software-defined DVB-T2 receiver; Demodulation; Digital video broadcasting; Interpolation; Program processors; Receivers; Standards;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics (ICCE), 2013 IEEE International Conference on

Conference_Location

Las Vegas, NV

ISSN

2158-3994

Print_ISBN

978-1-4673-1361-2

Type

conf

DOI

10.1109/ICCE.2013.6487026

Filename

6487026