DocumentCode
1692289
Title
Modeling the 3D self ballasting behavior and filamentation under high current stressing in DeNMOS
Author
Chatterjee, Amitabh ; Pendharkar, Sameer ; Duvvury, Charvaka ; Brewer, Forrest
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of California, Santa Barbara, CA, USA
fYear
2011
Firstpage
164
Lastpage
167
Abstract
A critical understanding of self ballasting behavior due to current crowding of avalanche generated carriers in a DeNMOS is developed. Then we study its performance under the gate biased conditions. The impact of flow of holes and electron in the bulk and across the surface - on the snapback-back features has been critically evaluated through variations in the device structure (associated with process parameter) which has also been extensively studied through 2D & 3D TCAD simulations. We demonstrate that after an initial homogeneous triggering (due to bipolar snapback), self heating preferentially activates the 2D array of bipolars in the bulk and subsequently current instability under negative resistance regime (as the bipolar turns on) leads to inhomogeneous triggering in the 3D.
Keywords
MIS devices; semiconductor device models; stability; technology CAD (electronics); 2D TCAD simulations; 3D TCAD simulations; 3D self ballasting; DeNMOS; avalanche generated carriers; bipolar snapback; current crowding; current instability; device structure; filamentation; gate biased conditions; high current stressing; homogeneous triggering; negative resistance regime; snapback-back features; Charge carrier processes; Electronic ballasts; Electrostatic discharge; Logic gates; Proximity effect; Surface treatment; Three dimensional displays;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Semiconductor Devices and ICs (ISPSD), 2011 IEEE 23rd International Symposium on
Conference_Location
San Diego, CA
ISSN
1943-653X
Print_ISBN
978-1-4244-8425-6
Type
conf
DOI
10.1109/ISPSD.2011.5890816
Filename
5890816
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