DocumentCode :
1692346
Title :
Integration of 100V LDMOS devices in 0.35μm CMOS technology
Author :
Kong, Soon Tat ; Stribley, Paul ; Lee, Chris ; Ong, Michaelina
Author_Institution :
X-FAB Semicond. Foundries AG, Plymouth, UK
fYear :
2011
Firstpage :
176
Lastpage :
179
Abstract :
Successful integration of 100V LDMOS devices in 0.35μm CMOS technology is presented in this paper. These integrated devices are enhanced N-type and P-type LDMOS which are compatible with thin (14nm) and thick (40nm) layers of gate oxide. A breakdown voltage of more than 100V with RDS (ON) =200/180mΩ.mm2 for N-type LDMOS and RDS (ON) =690/640mΩ.mm2 for P-type LDMOS with 14nm/40nm gate oxide thickness.
Keywords :
CMOS integrated circuits; MOSFET; electric breakdown; CMOS technology; LDMOS devices; breakdown voltage; gate oxide; integrated devices; n-type LDMOS; p-type LDMOS; size 0.35 mum; voltage 100 V; 1f noise; Integrated circuit modeling; Logic gates; Resistance; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Power Semiconductor Devices and ICs (ISPSD), 2011 IEEE 23rd International Symposium on
Conference_Location :
San Diego, CA
ISSN :
1943-653X
Print_ISBN :
978-1-4244-8425-6
Type :
conf
DOI :
10.1109/ISPSD.2011.5890819
Filename :
5890819
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=1692346
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