DocumentCode
1692414
Title
High performance in Network-on-Chip using efficient routing
Author
Prabhu, V. ; Ramachandran, R.
Author_Institution
ECE, Veltech MultitechDr.RangarajanDr.Sakunthala Engg.Coll., Chennai, India
fYear
2010
Firstpage
216
Lastpage
221
Abstract
The performance of Network-on-Chip largely depends on the underlying routing techniques, which have two constituencies: output selection and input selection. Previous research on routing techniques for Network on chip has focused on the improvement of output selection. This paper investigates the impact of input selection, and presents a novel contention-aware input selection technique for network on chip that improves the routing efficiency. When there are contentions of multiple input channels competing for the same output channel, Contention-aware input selection decides which input channel obtains the access depending on the contention level of the upstream switches, which inturn removes possible network congestion. Simulation results with different synthetic and real-life traffic patterns show that, when combined with either deterministic or adaptive output selection, Contention -aware input selection achieves significant better performance than the traditional first-come-first-served input selection, with low hardware overhead.
Keywords
network routing; network-on-chip; contention level; contention-aware input selection; hardware overhead; network congestion; network routing; network-on-chip; routing efficiency; Codecs; Color; Computer aided instruction; Routing; Switches; CAIS; CL; FCFS; NoC; OE; OS;
fLanguage
English
Publisher
ieee
Conference_Titel
Communication Control and Computing Technologies (ICCCCT), 2010 IEEE International Conference on
Conference_Location
Ramanathapuram
Print_ISBN
978-1-4244-7769-2
Type
conf
DOI
10.1109/ICCCCT.2010.5670554
Filename
5670554
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