HW/SW architecture for speech recognition acceleration

Author

Fastow, R. ; Rosner, Sonke ; Natarajan, Vivek ; Hasan, Q. ; Olson, Joe ; Unseld, M. ; Feng Liu ; Chendra, H. ; Bapat, O. ; Chen Liu

Author_Institution

Spansion, Inc., Sunnyvale, CA, USA

fYear

2013

Firstpage

608

Lastpage

609

Abstract

This paper describes a new hardware architecture for fast Acoustic Model scoring in embedded speech recognition systems by integrating an 8-way data-path with a NOR Flash array. This architecture localizes computation of critical algorithms and reduces decode latency and CPU load by 50% for large acoustic models, resulting in lower word error rates for natural language speech recognition.

Keywords

speech coding; speech recognition; 8-way data-path; CPU load; HW-SW architecture; NOR Flash array; acoustic model; decode latency reduction; embedded speech recognition systems; natural language speech recognition; speech recognition acceleration; word error rates; Acoustics; Bandwidth; Brain modeling; Computational modeling; Computer architecture; Hidden Markov models; Speech recognition;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics (ICCE), 2013 IEEE International Conference on

Conference_Location

Las Vegas, NV

ISSN

2158-3994

Print_ISBN

978-1-4673-1361-2

Type

conf

DOI

10.1109/ICCE.2013.6487038

Filename

6487038

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1692549