Investigation of parasitic BJT turn-on enhanced two-stage drain saturation current in high-voltage NLDMOS

Author

Cheng, Chih-Chang ; Chou, H.L. ; Chu, F.Y. ; Liou, R.S. ; Lin, Y.C. ; Wu, K.M. ; Jong, Y.C. ; Tsai, C.L. ; Cai, Jun ; Tuan, H.C.

Author_Institution

Analog/RF & Specialty Technol. Div., Taiwan Semicond. Manuf. Co. (TSMC), Hsinchu, Taiwan

fYear

2011

Firstpage

208

Lastpage

210

Abstract

A two-stage drain current phenomenon in saturation region, named as I_d-V_d hump, has been investigated in high-voltage NMOS transistor. A parasitic BJT turn-on enhanced I_d-V_d hump model is proposed and characterized by using a two-dimensional device simulation. By optimizing channel/drift-region process conditions, both parasitic BJT and impact-ionization generation can be suppressed. Both measured result and simulated result of the optimized device are presented.

Keywords

MOSFET; bipolar transistors; impact ionisation; semiconductor device models; channel/drift-region; high-voltage NLDMOS; high-voltage NMOS transistor; impact-ionization generation; parasitic BJT turn-on; two-dimensional device simulation; two-stage drain saturation current; Charge carrier processes; Electric potential; Logic gates; Optimization; Resistance; Semiconductor process modeling; Simulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs (ISPSD), 2011 IEEE 23rd International Symposium on

Conference_Location

San Diego, CA

ISSN

1943-653X

Print_ISBN

978-1-4244-8425-6

Type

conf

DOI

10.1109/ISPSD.2011.5890827

Filename

5890827