Title :
A versatile 30V analog CMOS process in a 0.18μm technology for power management application
Author :
Choi, Yong-Keon ; Park, Il-Yong ; Lim, Hyun-Chol ; Kim, Mi-Young ; Yoon, Chul-Jin ; Kim, Nam-Joo ; Yoo, Kwang-Dong ; Hutter, Lou N.
Author_Institution :
Analog Foundry Bus. Unit, Dongbu HiTek, Bucheon, South Korea
Abstract :
A versatile 30V analog CMOS process in a 0.18 μm technology node has been developed by using cost-effective and modular fashion. To reduce the thermal budget deep NWELL isolation is formed after CMOS well formation. The drain-extended (DE) CMOS from 7V to 30V shows very competitive trade-off performance between the breakdown voltage and the specific on-resistance. In addition, low 1/f noise of 5V CMOS can be obtained by pure gate oxide process.
Keywords :
1/f noise; CMOS integrated circuits; low-power electronics; 1/f noise; CMOS well formation; analog CMOS process; deep NWELL isolation; drain-extended CMOS; power management application; pure gate oxide process; size 0.18 mum; voltage 30 V; voltage 5 V; Analog circuits; CMOS integrated circuits; CMOS technology; EPROM; Logic gates; Noise; Transistors;
Conference_Titel :
Power Semiconductor Devices and ICs (ISPSD), 2011 IEEE 23rd International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4244-8425-6
DOI :
10.1109/ISPSD.2011.5890830
