Title :
Residual charge on the faulty floating gate CMOS transistor
Author_Institution :
Sch. of Eng., Durham Univ., UK
Abstract :
A common defect that can occur in CMOS integrated circuits is a break in a signal track. The effect of this defect is strongly dependent on the amount of charge trapped on the isolated MOS transistor gate. Results of measurements on test structures are presented which reveal a range of values for the trapped charge. This causes the resulting fault to have a widely varying effect on circuit performance. A test strategy which guarantees detection of such faults is proposed
Keywords :
CMOS integrated circuits; fault location; integrated circuit testing; logic testing; voltage measurement; CMOS integrated circuits; circuit performance; defect; fault detection; faulty floating gate CMOS transistor; isolated MOS transistor gate; residual charge; signal track; trapped charge; CMOS integrated circuits; Charge measurement; Circuit faults; Circuit optimization; Circuit testing; Current measurement; Electrical fault detection; Fault detection; Integrated circuit measurements; MOSFETs;
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2103-0
DOI :
10.1109/TEST.1994.527999
