Methodologies for fast yield ramp with limited engineering resources utilizing Inline Defect data overlay to SRAM Bitmap failure and Logic Diagnostics

Yield ramp is a significant metric in determining the profitability of the semiconductor industry. Defect inspection methodologies play a major role in detecting key defect modes inline before functional testing. A fast, production ready Yield learning methodology is needed to quantify the impact of inline detected and non-detected defects and to provide a way of determining the priority of processes. This information helps the engineering teams to highlight critical yield-limiting defects and facilitate an understanding of failure modes. Current conventional strategies have limitations of inaccuracy and larger cycle time. The methodologies presented in this paper utilize Inline Defect data overlay to SRAM Bitmap failure and Logic Diagnostics for fast yield ramp in limited engineering resources. These methodologies have demonstrated exceptional cycle time reduction on cutting edge 28nm, 20nm and 14nm test chips including customer products.