Title :
Reliability and performance optimization of 42V N-channel drift MOS transistor in advanced BCD technology
Author :
Molfese, A. ; Gattari, P. ; Marchesi, G. ; Croce, G. ; Pizzo, G. ; Alagi, F. ; Borella, F.
Author_Institution :
Technol. R&D, STMicroelectron., Agrate Brianza, Italy
Abstract :
Optimization flow for a 42V N-channel drift MOS in an advanced BCD technology in terms of performance and stability is described. The origin of the very fast on state resistance (Ron) degradation detected during reliability tests under off state on the starting device has been identified in borderless silicon nitride used as stop layer during contact etch. The final solution including a process step introduction, device geometry modification and drain doping profile optimization improves performance and addresses both voltage capability and reliability requirements.
Keywords :
MOSFET; etching; optimisation; reliability; semiconductor doping; N-channel drift MOS transistor; advanced BCD technology; contact etch; device geometry modification; drain doping profile optimization; reliability; stability; voltage 42 V; Buffer layers; Degradation; Logic gates; Optimization; Performance evaluation; Reliability; Stress;
Conference_Titel :
Power Semiconductor Devices and ICs (ISPSD), 2011 IEEE 23rd International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4244-8425-6
DOI :
10.1109/ISPSD.2011.5890860
