Title :
Is IDDQ yield loss inevitable?
Author_Institution :
AT&T Bell Labs., Princeton, NJ, USA
Abstract :
IDDQ testing is a powerful way to improve the quality of low fault coverage tests, and to detect defects that are hard or impossible to detect using traditional voltage testing methods. However, it appears that there is some yield loss associated with IDDQ testing, where yield loss means that devices passing burn-in and system tests fail IDDQ test. This paper gives reasons why such yield loss is inevitable, and must be considered when making a decision whether or not to use IDDQ testing. We also present some evidence backing up this speculation, and a brief economic model to help in making IDDQ testing decisions
Keywords :
CMOS logic circuits; economics; electric current measurement; fault diagnosis; integrated circuit yield; logic testing; CMOS IC; IDDQ testing; IDDQ yield loss; burn-in; decision making; defense equipment; delay faults; economic model; electronic toy; logic testing; low fault coverage test; system tests; CMOS integrated circuits; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Fixtures; Integrated circuit testing; Logic testing; System testing; Voltage;
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2103-0
DOI :
10.1109/TEST.1994.528001
