The effect of backside roughness on Al interconnect dimensions for RF CMOS SOI devices

Backside roughness variation on incoming Silicon-On-Insulator (SOI) wafers can cause systematic variations in the dimensions of Al interconnects. Wafers with more backside roughness are more effectively cooled during reactive ion etching (RIE), resulting in a lower wafer temperature during the etch, and a larger line width. The backside roughness of the SOI substrate must be considered in order to minimize wafer-to-wafer variations in the Al linewidth.