The effect of backside roughness on Al interconnect dimensions for RF CMOS SOI devices

Author

Moon, Matthew D. ; Gambino, Jeffrey P. ; Adderly, Shawn A. ; Hanrahan, Jeffrey ; Cucci, Brett

Author_Institution

Microelectron. Div., IBM, Essex Junction, VT, USA

fYear

2014

fDate

19-21 May 2014

Firstpage

384

Lastpage

388

Abstract

Backside roughness variation on incoming Silicon-On-Insulator (SOI) wafers can cause systematic variations in the dimensions of Al interconnects. Wafers with more backside roughness are more effectively cooled during reactive ion etching (RIE), resulting in a lower wafer temperature during the etch, and a larger line width. The backside roughness of the SOI substrate must be considered in order to minimize wafer-to-wafer variations in the Al linewidth.

Keywords

CMOS integrated circuits; aluminium; integrated circuit interconnections; silicon-on-insulator; sputter etching; Al; Al interconnect dimensions; Al linewidth; RF CMOS SOI devices; RIE; SOI substrate; Si; backside roughness variation; reactive ion etching; silicon-on-insulator wafers; systematic variations; wafer temperature; wafer-to-wafer variations; Integrated circuit interconnections; Metals; Radio frequency; Resistance; Silicon; Silicon-on-insulator; Substrates; Backside Roughness; Etch Sensitivity; Front-End-Module; Power Amplifier; SOI; SOI RF; Semiconductor Materials; Substrate Differences;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference (ASMC), 2014 25th Annual SEMI

Conference_Location

Saratoga Springs, NY

Type

conf

DOI

10.1109/ASMC.2014.6846960

Filename

6846960