High-K metal gate contact process optimization for yield improvement via innovative defect inspection technique

High-K metal gate processes induce new process and wafer defect inspection challenges compared with traditional poly silicon. Mechanisms of two systematic yield-limiting defects at the contact loop process step are discussed. In addition, an innovative method of defect detection and contact process improvement for 28nm high-K metal gate process ramping is shared. The defect inspection strategy involved the use of e-Beam, broadband plasma optical and laser scanning optical inspectors. The new defect detection and process improvement method has demonstrated faster time to results with >90% defect reduction and a SRAM yield gain of >20%.