DocumentCode :
1693591
Title :
Design of an 80V-class high-side capable double-resurf JI L-IGBT
Author :
Fujii, Hiroki ; Komatsu, Shinichi ; Sato, Masaharu ; Ichikawa, Toshihiko
Author_Institution :
Devices & Anal. Technol. Div., Renesas Electron. Corp., Sagamihara, Japan
fYear :
2011
Firstpage :
372
Lastpage :
375
Abstract :
This paper proposes a suitable design of an 80V-class high-side capable double-resurf lateral IGBT (L-IGBT) using our cost-effective HV-MOS process, which excludes SOI/DTI structures. This junction-isolated (JI) L-IGBT, unlike a drift-NMOSFET, suffered a large substrate leakage caused by a parasitic PNP BJT whose collector was a p-substrate. It also had a disadvantage in turn-off time due to the floated n-drift layer. We tried a unique, promising approach - the p+ collector was connected to the outmost enclosing n+ sinker internally by n-drift region resistor and externally by metallization, which needs no additional process steps. Our measurement results show that it successfully eliminated both problems without almost any sacrifice in performance of current drivability per area, breakdown voltage, HCI, and ESD endurance.
Keywords :
MOSFET; insulated gate bipolar transistors; semiconductor device models; HV-MOS process; SOI/DTI structures; breakdown voltage; drift-NMOSFET; floated n-drift layer; high-side capable double-resurf JI L-IGBT; high-side capable double-resurf lateral IGBT; junction-isolated L-IGBT; large substrate leakage; n+ sinker; n-drift region resistor; p+ collector; p-substrate; parasitic PNP BJT; turn-off time; voltage 80 V; Electrostatic discharge; Integrated circuits; Layout; Logic gates; Resistance; Substrates; Voltage measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Power Semiconductor Devices and ICs (ISPSD), 2011 IEEE 23rd International Symposium on
Conference_Location :
San Diego, CA
ISSN :
1943-653X
Print_ISBN :
978-1-4244-8425-6
Type :
conf
DOI :
10.1109/ISPSD.2011.5890868
Filename :
5890868
Link To Document :
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