DocumentCode
1693794
Title
A novel, wafer-scale technology for addressing process and cost obstacles associated with underfilling FCOB
Author
Burress, Robert V. ; Capote, M. Albert ; Lee, Yong-Joon ; Lenos, Howard A. ; Zamora, Jeffrey F.
Author_Institution
Aguila Technol. Inc., San Marcos, CA, USA
fYear
2002
fDate
6/24/1905 12:00:00 AM
Firstpage
386
Lastpage
389
Abstract
This paper provides an update on development work underway to produce a novel wafer-scale packaging technology. The technology, referred to as multi-layer, wafer-scale encapsulation (MLWSE), relies on high performance polymers which are used in wafer-level encapsulation and subsequent electronic assembly processes. High-speed laser processing, which is used to produce the interconnection structure, is another integral aspect of this technology. We will describe the basic elements of the technology and present the current state of development with data from test assemblies. Also to be discussed are the potential technological/assembly benefits offered by the MLWSE technology and a summary of the results of a cost analysis comparing this technology to other HDI technologies.
Keywords
chip-on-board packaging; encapsulation; flip-chip devices; integrated circuit interconnections; integrated circuit packaging; laser beam applications; wafer-scale integration; MLWSE; cost analysis; electronic assembly; flip-chip; high performance polymers; high-speed laser processing; interconnection structure; multi-layer wafer-scale encapsulation; underfilling FCOB; wafer-scale packaging technology; wafer-scale technology; Assembly; Costs; Electronics packaging; Encapsulation; Flip chip; Optical materials; Polymers; Space technology; Stress; Surface-mount technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference, 2002. Proceedings. 52nd
ISSN
0569-5503
Print_ISBN
0-7803-7430-4
Type
conf
DOI
10.1109/ECTC.2002.1008125
Filename
1008125
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