Novel materials and processes for wafer pre-apply flip chip and chip scale packaging

This paper investigated the feasibility of an exploratory "wafer dual encapsulation" process for flip chip and chip scale (FC/CSP) packaging. This process involves two different encapsulant materials which are applied in two different processing steps. This systematic study identified potential challenges both in material and process and demonstrated corresponding solutions. A complete "wafer dual encapsulation" process, from material deposition onto wafer to individual chip attachment onto substrate, has been explored and optimized. A thorough study on material requirements suitable for this wafer dual encapsulation process was conducted. The required material properties of the two types of encapsulant materials were identified. Based on this study, two sets of novel encapsulant materials met the required material properties for enhanced reliability and demonstrated process convenience for flip chip and CSP packaging. The "wafer dual encapsulation" process and the encapsulant materials designed for this process are fully compatible to current surface mount technology (SMT).