MOS device structure development for ULSI: low power/high speed operation

The historical development of MOS structures was briefly reviewed and its trend also examined. On the basis of this consideration, the new MOS device structure, INSEC (I_n_trinsic S_ilicon E_pi-C_hannel) MOSFET was proposed for low power/high speed operation. The concept of the INSEC MOSFET is to reduce the subthreshold swing by introducing a thin intrinsic epitaxial silicon layer into the channel with a high impurity concentration. By this method, we can reduce the threshold voltage without any increase in the off-state leakage current and reduce the lateral electric field significantly. DIBL (drain-induced barrier lowering) can be suppressed successfully by controlling the channel impurity concentration below the intrinsic silicon epi-layer. The INSEC MOSFET can be operated with high performances even at the scaled supply voltage by controling its intrinsic epi-layer thickness