450 mm carrier interoperability effects on particle Generation

The semiconductor industry continues to scale up silicon wafer size in an effort to drive lower costs associated with high volume manufacturing. This effort has begun in earnest at the SUNY College of Nanoscale Science and Engineering, driven by the Global 450 mm Consortium (G450C). The focus of the G450C is to be a public-private partnership (CNSE, Intel, TSMC, Samsung, IBM and GLOBALFOUNDRIES) that develops cost-effective test wafer fabrication infrastructure, equipment prototypes and high-volume tools to enable a coordinated industry transition to the next silicon wafer size. This includes discovering and remedying challenges in carrier efficacy in maintaining wafer cleanliness through wafer and carrier testing and measurement within the G450C equipment and fab infrastructure. The authors will discuss the current status of 450 mm carrier, wafer, and equipment learning and improvements towards reducing or eliminating the defectivity contributions of carrier components and carrier/tool interoperability, including the contribution of automated material handling systems (AMHS).