Keynote Speech 1

Summary form only given. SRAM designers have recognized that threshold-voltage (Vth) variation is the most serious issue to enable further area and operating-voltage (Vdd) scaling. Various circuit design techniques to address this issue have attracted much attention at leading edge conferences since 65 nm process node, but their extendibility for 22 nm and beyond have not been reviewed and compared. The transition now between 32 nm and 22 nm technology nodes provides the right opportunity to give an expert evaluation of which techniques will become the mainstream for various applications. This talk discusses and compares area-scaling-capabilities of many kinds of SRAM margin-assist solutions for V_T variability issues, which are based on various efforts by not only the cell topology changes from 6T to 8T and 10T but also incorporating of multiple voltage supply for cell terminal biasing and timing sequence controls of read and write. The various SRAM solutions are reviewed and analyzed in light of an impact on the required area overhead for each design solution given by ever increasing V_T-random variation (sigma_VT), resulting in a slowdown in the SRAM scaling pace. In order to predict the area scaling trends among various SRAM solutions, two different sigma_VT-increasing scenarios of being pessimistic and optimistic are assumed where sigma_VT becomes >130 mV or suppressed to <70 mV at 15 nm process node, respectively. As a result, it has been shown that 6T SRAM cell will be allowed a long reign even in 15 nm process node if sigma_VT can be suppressed to <70 mV thanks to EOT (Effective Oxide Thickness) scaling even for LSTP (Low Standby Power) process technologies, otherwise 10T and 8T with read modify write (RMW) will be needed after sigma_VT becomes >85 mV and 75 mV, respectively. This talk also gives some examples for a required paradigm shift in SRAM circuit designs to tackle- ever increasing serious issues for further area and Vdd scaling.