Design of an energy-efficient 32-bit adder operating at subthreshold voltages in 45-nm CMOS

Low-power circuits is quickly increasing their importance due to the high cost in design of cooling systems with complex chip packaging techniques, and also due to the low energy consumption requirement of portable devices powered by a limited battery capacity. This paper presents design of a low-power 32-bit adder that is a basic functional unit in most computational platforms. Its energy efficiency is highly achieved while operating in the subthreshold regime. Simulation results in 45-nm PTM CMOS show the adder consumes only 22 fJ per computation at 0.2 V with maximum operating frequency of 3.8 MHz. While targeting an acceptable frequency of 100 MHz, it consumes only 3.4 μW or 34 fJ per computation at 0.37 V. At 1.0 V, it can operate at up to 2.85 GHz while consuming only 735 μW or 257 fJ per computation. It also stably operates at only 0.1 V with throughput of 400 kHz and consumes 18 nW.