Title :
Multilevel logic synthesis using algorithms based on natural processes
Author :
Sánchez, J.M. ; Lanchares, J.
Author_Institution :
Dept. of Comput. Sci. & Automatics, Madrid Univ., Spain
Abstract :
In this paper we address the optimization problem of multilevel logical functions using algorithms based on natural process. We show the results found by applying the simulated annealing algorithm and a genetic algorithm to area optimization of multilevel logical networks using the IWLS´93 benchmarks
Keywords :
circuit layout CAD; circuit optimisation; genetic algorithms; integrated circuit layout; integrated logic circuits; logic CAD; multivalued logic circuits; simulated annealing; area optimization; genetic algorithm; multilevel logic synthesis; multilevel logical functions; optimization problem; simulated annealing algorithm; Cost function; Design optimization; Genetic algorithms; Genetic mutations; Heuristic algorithms; Logic functions; Organisms; Silicon; Simulated annealing; Thermodynamics;
Conference_Titel :
Microelectronics, 1995. Proceedings., 1995 20th International Conference on
Conference_Location :
Nis
Print_ISBN :
0-7803-2786-1
DOI :
10.1109/ICMEL.1995.500975
