• DocumentCode
    1695160
  • Title

    Direct bump-on-copper process for flip chip technologies

  • Author

    Ling, Jamin ; Sanchez, Joseph ; Moyer, Ralph ; Bachman, Mark ; Stepniak, Dave ; Elenius, Pete

  • Author_Institution
    Flip Chip Div., Kulicke & Soffa, Phoenix, AZ, USA
  • fYear
    2002
  • fDate
    6/24/1905 12:00:00 AM
  • Firstpage
    704
  • Lastpage
    710
  • Abstract
    Direct bump-on-copper technology provides a direct cost saving, equivalent bumping qualities, and better performance and reliability for products. The bump-on-copper FOC (flex-on-cap) technology is modified and derived from the existing high volume, reliable, proven bump-on-aluminum FOC process. A copper compatible adhesion layer, namely, titanium, combined with a NiV barrier layer and a Cu wetting layer for solder are used to construct the tri-metal stack that defines a reliable under bump metallurgy (UBM) for flip chip solder bumps. A proprietary solder deposition technique using solder paste is then applied to form the solder interconnects. Bump quality tests such as bump height and bump shear strength demonstrates an equivalent structure to the existing Al/NiV/Cu based flip chip bump. Wafers constructed as described are tested at both wafer level and in an assembled level. All perform well in the preliminary reliability evaluation including temperature cycle (TC), thermal shock (TS), autoclave test (PCT), high temperature storage (HTS), high temperature operational life (HTOL), and high accelerated stress test (HAST).
  • Keywords
    adhesion; flip-chip devices; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; life testing; reflow soldering; shear strength; Al-NiV-Cu; FOC; adhesion layer; autoclave test; bump height; bump shear strength; bumping qualities; direct bump-on-copper process; equivalent structure; flex-on-cap technology; flip chip solder bumps; flip chip technologies; high accelerated stress test; high temperature operational life; high temperature storage; reliability; reliability evaluation; solder deposition technique; solder interconnects; solder paste; temperature cycle test; thermal shock test; tri-metal stack; under bump metallurgy; wafer level; Adhesives; Assembly; Copper; Costs; Flip chip; Life testing; Performance evaluation; Temperature; Thermal stresses; Titanium;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2002. Proceedings. 52nd
  • ISSN
    0569-5503
  • Print_ISBN
    0-7803-7430-4
  • Type

    conf

  • DOI
    10.1109/ECTC.2002.1008175
  • Filename
    1008175