Title :
Modelling and performance analysis of digital baseband processor of the GPS receiver
Author :
Zhuang, Weihua ; Murthy, K. M Sundara
Author_Institution :
Dept. of Electr. Eng., Ottawa Univ., Ont., Canada
Abstract :
A global positioning system (GPS) receiver has been modelled and implemented in software. A digital full-time delay lock loop (DDLL) is designed for the pseudorange time delay measurement and a digital phase-locked loop (DPLL) is applied for measurements of the carrier beat phase and Doppler shift. The closed form expressions of the detection and false-alarm probabilities for the code phase acquisition process and the variance of the code phase tracking error for the code phase fine synchronization process are derived. The performance of the modelled static receivers is validated by computer simulations
Keywords :
Doppler effect; digital radio systems; digital simulation; phase-locked loops; radio receivers; radionavigation; satellite relay systems; signal processing; telecommunications computing; DDLL; DPLL; Doppler shift; GPS receiver; carrier beat phase measurement; closed form expressions; code phase acquisition; code phase fine synchronization; code phase tracking error; computer simulations; digital baseband processor; digital full-time delay lock loop; digital phase-locked loop; false-alarm probability detection; global positioning system; performance analysis; pseudorange time delay measurement; software; Baseband; Delay effects; Doppler shift; Global Positioning System; Performance analysis; Phase detection; Phase locked loops; Phase measurement; Time measurement; Tracking loops;
Conference_Titel :
Personal, Indoor and Mobile Radio Communications, 1992. Proceedings, PIMRC '92., Third IEEE International Symposium on
Conference_Location :
Boston, MA
Print_ISBN :
0-7803-0841-7
DOI :
10.1109/PIMRC.1992.279904
