A 10-bit CMOS 300 MHz Current-Steering D/A Converter

In this paper, a 10-bit 300 MHz current-steering D/A converter in 0.35-mum CMOS is presented. Running from a single 3.3V power supply, it has a power consumption of 100mW for an clock signal of 300MHz for the use of the limited current cell switch matrix. In order to ensure the linearity of DAC, a double Centro symmetric current matrix is designed by using the Q² random walk strategy. With the 6 most significant bits (MSBs) being implemented as equally weighted current sources, high linearity has been achieved. Differential nonlinearity (DNL) of 0.6 LSB and integral nonlinearity (INL) of 0.6 LSB have been measured. To achieve better dynamic performance, a latch and a buffer have been added in front of the current switch to change the input signal, such as its optimal cross-point and voltage level. For a 10-bit resolution, the converter has reached an update rate of 300MHz.