Title :
Design and Implementation of a High-Speed Reconfigurable Feedback Shift Register
Author :
Dai, Zibin ; Li, Wei ; Chen, Tao ; Ren, Qiao
Author_Institution :
Inst. of Electron. Technol., Univ. Zhengzhou, Zhengzhou
Abstract :
A high-performance and dynamic reconfigurable feedback shift register is presented, which provides full support to linear and nonlinear feedback shift register. The architecture can be also reconfigured any lengths, feedback taps and feedback function. To save the hardware cost and get shorter critical path, we proposed EXCLUSIVE-OR tree network to implement linear feedback function, and put forward AND-OR tree network to optimize nonlinear feedback function. The design has been realized using Altera´s FPGA. Synthesis, placement and routing of reconfigurable design have accomplished on 0.18 mum CMOS process. The result proves that the propagation time of reconfigurable feedback shift register with 256 lengths is 3.28ns. Compared with other designs, the architecture can achieve relatively high flexibility, furthermore, it has an obvious advantage in the aspect of speed.
Keywords :
CMOS logic circuits; field programmable gate arrays; logic design; logic gates; network routing; shift registers; AND-OR tree network; CMOS; EXCLUSIVE-OR tree network; FPGA; dynamic reconfigurable feedback shift register; nonlinear feedback function; reconfigurable design placement; reconfigurable design routing; reconfigurable design synthesis; size 0.18 mum; time 3.28 ns; Application specific integrated circuits; Cost function; Cryptography; Design engineering; Feedback; Field programmable gate arrays; Hardware; Network synthesis; Reconfigurable logic; Shift registers;
Conference_Titel :
Circuits and Systems for Communications, 2008. ICCSC 2008. 4th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-1707-0
Electronic_ISBN :
978-1-4244-1708-7
DOI :
10.1109/ICCSC.2008.79
