Die attach delamination characterization modeling for SOIC package

Die attach delamination is a critical reliability problem which may cause thermal management and electrical issues, and can further increase the risk of contamination-related failure and stitch bond failures. In this paper, die attach delamination of a SOIC package is simulated and analyzed by 2D/3D FEA. Two major analyses for pre-delamination and post-delamination are investigated. Modeling includes the 3D moisture diffusion under 85C/60%RH, thermal stresses in different die, die pad and die attach dimensions, and characterizes the influence of these dimensions on die attach delamination at 260 degrees C reflow temperatures. Another investigation is the post-delamination analysis, in which an initial crack is assumed. The strain energy release, CTE stresses and effects of moisture vapor pressure for different die attach thickness, different defect positions and different crack lengths are studied. An effective interfacial layer delamination formulation is introduced to determine the delamination parameters, which may avoid the oscillations of the solution for crack tip stress and the invalidation of the J integral when the crack surface is subjected to the vapor pressure.