Low power mode and IEEE 1149.1 compliance: a low power solution

Author

Crouch, Alfred L. ; Ramus, Rick ; Maunder, Colin

Author_Institution

Motorola Inc., Austin, TX, USA

fYear

34608

Firstpage

660

Lastpage

669

Abstract

The requirements of a low power mode, built into complex VLSI IC´s such as microprocessors, seem to conflict with the IEEE 1149.1 Standard (JTAG). The perception that the TAP Pins-T¯R¯S¯T¯, TMS, and TDI-must be equipped with power-consuming pullup resistors or that low power and 1149.1 modes of operation are mutually exclusive is erroneous. Certain techniques can be used during the design and implementation of the TAP and the TAP controller that will allow the IC to enter low power mode without interference or unnecessary power consumption from the JTAG logic and will allow JTAG operations during low power mode while maintaining full compliance to the 1149.1 standard

Keywords

CMOS integrated circuits; IEEE standards; VLSI; computer testing; integrated circuit testing; microprocessor chips; CMOS; IEEE 1149.1 compliance; JTAG logic; MC68060; TAP Pins; TDI; TMS; TRST; complex VLSI IC; low power mode; microprocessors; power-consuming pullup resistors; Batteries; CMOS technology; Energy consumption; Logic design; Logic devices; Logic testing; Microprocessors; Pins; Standards development; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1994. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-2103-0

Type

conf

DOI

10.1109/TEST.1994.528011

Filename

528011