DocumentCode :
1696310
Title :
Optimal design of an integrated substrate based on the analysis of warpage and delamination propagation
Author :
Hurang Hua ; Sitaraman, Suresh K.
Author_Institution :
Dept. of Eng., Clark Atlanta Univ., GA, USA
fYear :
2002
fDate :
6/24/1905 12:00:00 AM
Firstpage :
941
Lastpage :
946
Abstract :
A next-generation packaging concept, "System-On-Package (SOP)", is being developed at Georgia Tech. At the heart of the SOP is a fully integrated substrate with ultra high-density wiring, buried capacitor, inductor, resistor and optoelectronic layers on top of a base substrate. During fabrication as well as under working conditions, severe warpage and stresses could arise in the SOP substrate due to the temperature gradients and the CTE mismatch among its different constituent materials. For the SOP integrated substrate, five materials are being considered as the candidate material for the base substrate on which thin film layers will be sequentially processed. These candidate base substrate materials are glass-epoxy composites FR-4, Ceramic cloth/FR-4 resin (Ceramic/FR-4), Carbon cloth+Carbon filler/FR-4 resin (Carbon/FR-4), Carbon cloth/Cyanate easter resin (Carbon/Cyanate), and metal matrix composites AlSiC. In this study, the thermo-mechanical reliability of the SOP substrate with these five candidate base substrate materials is evaluated. The focus of the research is on the SOP substrate warpage and fatigue interlayer delamination propagation under thermal shock. It is found that the warpage is directly proportional to the thermal load. A comparison study of the substrate with and without a silicon flip-chip assembly is also conducted. The study shows that there will be no delamination propagation for the SOP substrate both with and without a flip-chip assembly, however, a potential fatigue crack growth exists for all the substrates under the thermal shock. A comparison study of the SOP substrate under the two thermal shocks of -550C to 1250C and of -450C to 1200C is also made. The analysis results in this work may be used in optimal design of the SOP substrate.
Keywords :
delamination; fatigue cracks; flip-chip devices; packaging; reliability; substrates; thermal shock; -450 to 1200 C; -550 to 1250 C; Si; System-On-Package; delamination propagation; design optimization; fatigue crack; integrated substrate; silicon flip-chip assembly; thermal shock; thermomechanical reliability; warpage; Assembly; Ceramics; Delamination; Electric shock; Fatigue; Heart; Packaging; Resins; Substrates; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 2002. Proceedings. 52nd
ISSN :
0569-5503
Print_ISBN :
0-7803-7430-4
Type :
conf
DOI :
10.1109/ECTC.2002.1008214
Filename :
1008214
Link To Document :
بازگشت